Apu I/O access. Provides an ApuIo concept for reading and writing to APU I/O registers.
Types
ApuIo = concept var a ## Concept for a generic Apu emulator that provides I/O access procs. readRegister(a, uint8) is uint8 writeRegister(a, uint8, uint8)
- Source Edit
ApuRegister = enum ar10 = 16, ## NR10 -PPP NSSS - CH1 sweep period, negate, shift ar11 = 17, ## NR11 DDLL LLLL - CH1 duty, length ar12 = 18, ## NR12 VVVV APPP - CH1 envelope volume, mode, period ar13 = 19, ## NR13 FFFF FFFF - CH1 frequency LSB ar14 = 20, ## NR14 TL-- -FFF - CH1 trigger, length enable, frequency MSB ar21 = 22, ## NR21 DDLL LLLL - CH2 duty, length ar22 = 23, ## NR22 VVVV APPP - CH2 envelope volume, mode, period ar23 = 24, ## NR23 FFFF FFFF - CH2 frequency LSB ar24 = 25, ## NR24 TL-- -FFF - CH2 trigger, length enable, frequency MSB ar30 = 26, ## NR30 E--- ---- - CH3 DAC enable ar31 = 27, ## NR31 LLLL LLLL - CH3 length ar32 = 28, ## NR32 -VV- ---- - CH3 wave volume ar33 = 29, ## NR33 FFFF FFFF - CH3 frequency LSB ar34 = 30, ## NR34 TL-- -FFF - CH3 trigger, length enable, frequency MSB ar41 = 32, ## NR41 --LL LLLL - CH4 length ar42 = 33, ## NR42 VVVV APPP - CH4 envelope volume, mode, period ar43 = 34, ## NR43 SSSS WDDD - CH4 clock shift, width, divisor mode ar44 = 35, ## NR44 TL-- ---- - CH4 trigger, length enable ar50 = 36, ## NR50 ALLL BRRR - VIN enable (A/B), master volume (L/R) ar51 = 37, ## NR51 4321 4321 - Channel terminal enables ar52 = 38, ## NR52 P--- 4321 - Power control, channel length status arWaveram = 48 ## CH3 Wave RAM, 0xFF30 to 0xFF3F
- Enum for Apu register addresses. Source Edit
Templates
template toAddress(reg: ApuRegister): uint8
- Convert the register to its address. This just converts the result of ord to an uint8. Source Edit